The semiconductor industry has experienced continued rapid growth due to continuous improvements in the integration density of various electronic components. These integration improvements are generally two-dimensional (2D) in nature, that is, the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. FIG. 8 is a schematic view of a conventional 2D integrated circuit (IC) 800. With reference to FIG. 8, a semiconductor package 802 is connected to a die or chip 804 by way of solder balls or bumps 806. Those of skill in the art will readily recognize that other packaging materials can be connected to the package 802 in place of the chip 804. Further, the number of solder balls or bumps shown is only for illustrative purpose. Those of skill in the art will readily recognize that there are many variations which implement equivalent functions and the illustrative schematic view is made for illustrative purpose only. While improvements in lithography techniques have resulted in improvements in 2DIC formation, there are physical limits to the density that can be achieved in two dimensions.
Three-dimensional (3D) ICs resolve these physical limitations. A 3DIC is generally a semiconductor chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. FIG. 9 is a schematic view of a conventional 3DIC 900. With reference to FIG. 9, a semiconductor package 902 is connected to a tier 1 die or chip 904 by way of solder balls or bumps 906. The terms die and chip are used interchangeably herein and such use should not limit the scope of the claims appended herewith. The tier 1 chip 904 is then connected to a tier 2 chip 908 using through-substrate vias (TSVs) 910. In a typical formation process for a 3DIC, two wafers, each including an integrated circuit, are formed. The wafers are then bonded with the devices aligned. TSVs are formed to interconnect devices on the first and second substrates. In a die-on-wafer fabrication technique, electronic components are built on two semiconductor wafers. One wafer is diced, and the single dies are aligned and bonded onto die sites of the second wafer. Thinning and TSV creation are performed either before or after bonding, and additional dies can be added to the stacks before dicing. In a die-on-die fabrication technique, electronic components are built on multiple dies which are then aligned and bonded. Thinning and TSV creation are performed either before or after bonding. A 3DIC is a single chip whereby components on the respective layers communicate with on-chip signaling, vertically or horizontally. Using 3DIC technology, higher device density has been achieved than 2DIC technology. As a result of this increase in density, total wire length and number of vias are reduced.
Electrostatic discharge (ESD) is generally defined as a sudden and momentary electric current that flows between two objects at different electrical potentials. ESD can damage devices fabricated on IC chips causing performance degradation or failures. One of many considerations for IC design is on-chip ESD protection; however, due to the ever-increasing requirements for higher speeds, smaller devices and product reliability, the significance of on-chip ESD protection is critical in IC design. Conventional methods of ESD protection utilize 2DIC protection devices for a 3DIC. There are, however, too many power domains in a 3DIC to protect the chip from ESD using conventional 2DIC protection devices.